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低电压内嵌式非挥发性记忆体元件之设计

阅读量:02021-12-29作者:王明凯来源:电资工程学类
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研究生: 王明凯
研究生(外文): Ming-Kai Wang
论文名称: 低电压内嵌式非挥发性记忆体元件之设计
论文名称(外文): Design of Low-Voltage Embedded Non-Volatile Memory Devices
指导教授: 林泓均
学位类别: 硕士
校院名称: 国立中兴大学
系所名称: 电机工程学系所
学门: 工程学门
学类: 电资工程学类
论文种类: 学术论文
论文出版年: 2009
毕业学年度: 97
语文别: 中文
论文页数: 119
中文关键词: 低电压、内嵌式、非挥发性记忆体
外文关键词: Low-Voltage、Embedded、Non-Volatile Memory Devices


近年来内嵌式的记忆体架构,已被广泛的应用在各种不同的系统上,而在密度、功率消耗以及记忆体容量上,必须不断的提高效能。而内嵌式的记忆体系统,设计重点在于是否能跟记忆体系统以外的电路,整合在相同的制程上。如果能使用相同的制程,而又不需要增加额外的光罩,不论在设计或是制造上,都会节省相当多的时间与成本。
本论文的研究目标是参考文献中所使用的一般CMOS制程的Single-Poly EEPROM记忆体结构与观念,除了继续探讨此结构在不同制程下的表现,并透过设计的新型结构OTP(One Time Programming)非挥发性记忆体元件,也搭配T-CAD ISE 10.0模拟平台环境中Sentaurus Structure Editor(Sentaurus SE)这套元件结构模拟工具与HSPICE电性模拟工具等,对此元件做详尽的介绍与动作原理分析,同时透过UMC 90nm制程的下线实作晶片及量测,运用各种MOS电晶体所设计的记忆体元件做OTP测试,以期找出适合的非挥发性记忆体操作条件。


In recent years, the embedded storage devices have been extensively applied to different systems. The density, power consumption and capacity are continually improved to enhance the performance. The key issue of embedded memory is to integrate the other circuit with the memory array in the same process technology without extra masks. That would reduce significant development time and fabrication cost.
The goal of this thesis is to investigate the memory structures and design concept of well-known single-poly EEPROM using the standard CMOS technology. In addition to continuously study the performance of the same structures in different process technology, the novel OTP(One Time Programming)non-volatile memory device was designed with the assistance of the simulation tools - T-CAD ISE 10.0 Sentaurus Structure Editor(Sentaurus SE)and HSPICE. The detailed introduction and analysis of its operation principles were also presented. Using UMC 90nm technology, many memory devices with various MOS transistors were fabricated and measured in order to find the appropriate OTP non-volatile memory operation conditions.


志 谢 i
中文摘要 ii
Abstract iii
目 录 iv
表 目 录 vi
图 目 录 vii
第一章 序 论 - 1 -
第一节 前 言 - 1 -
一、动态随机存取记忆体(DRAM) - 3 -
二、静态随机存取记忆体(SRAM) - 4 -
三、罩幕式唯读记忆体(Mask ROM) - 5 -
四、可程式唯读记忆体(Programmable ROM) - 7 -
五、可抹除且可程式之唯读记忆体(Erasable Programmable ROM) - 7 -
六、可电性抹除且可程式之唯读记忆体(Electrically EPROM) - 9 -
第二节 快闪记忆体简介 - 11 -
第三节 通道载子注入现象 - 14 -
一、快闪记忆体的物理机制 - 14 -
二、热载子效应(Hot Carries Effect) - 15 -
三、冷载子效应(Cold Carries Effect) - 20 -
第四节 论文内容简介 - 25 -


第二章 嵌入式非挥发性记忆体元件结构之研究 - 26 -
第一节 SONOS记忆体元件结构原理分析 - 27 -
一、SONOS元件结构原理分析 - 28 -
二、元件写入机制原理(Program) - 30 -
三、元件抹除机制原理(Erase) - 30 -
四、元件临界电压值(Threshold Voltage) - 34 -
第二节 EEPROM记忆体元件结构原理分析 - 36 -
一、EEPROM元件结构原理分析 - 36 -
二、元件写入机制原理(Program) - 40 -
三、元件抹除机制原理(Erase) - 42 -
第三节 MTP记忆体元件结构原理分析 - 43 -
一、MTP元件结构原理分析 - 43 -
二、元件写入机制原理(Program) - 46 -
三、元件抹除机制原理(Erase) - 49 -
四、电荷存储层(CSN)写入状态分析 - 51 -


第三章 低电压内嵌式非挥发性记忆体元件设计 - 55 -
第一节 SONOS记忆体元件设计与分析 - 57 -
一、SONOS元件结构设计与制程参数设定 - 57 -
二、模拟结果分析 - 61 -
第二节 EEPROM记忆体元件设计与分析 - 68 -
一、EEPROM元件结构设计与制程参数设定 - 69 -
二、模拟结果分析 - 73 -
第三节 OTP记忆体元件设计与分析 - 77 -
一、OTP元件结构设计与制程参数设定 - 78 -
二、模拟结果分析 - 82 -


第四章 元件量测结果与讨论 - 87 -
第一节 元件量测环境 - 88 -
第二节 EEPROM元件量测结果与分析 - 89 -
一、TSMC 0.35μm制程之记忆体元件量测结果 - 90 -
二、TSMC 0.25μm制程之记忆体元件量测结果 - 94 -
三、TSMC 0.18μm制程之记忆体元件量测结果 - 98 -
第三节 OTP元件量测结果与分析 - 103 -
一、UMC 90nm制程之OTP记忆体测试元件列表 - 104 -
二、UMC 90nm OTP记忆体测试元件写入状态时量测结果 - 108 -


第五章 未来规划与结论 - 115 -
第六章 参考文献 - 117 -


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